Timing-driven Placement
Timing-Driven Placement is a physical design methodology in electronic design automation that belongs to the class of placement techniques and is distinguished by its explicit optimization of component locations to meet timing constraints during the synthesis of integrated circuits.
154
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6.7K
Citations
357
Authors
92
Institutions
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2017–2026
12
154
Timing-driven placement for FPGAs
Alexander Marquardt, Vaughn Betz, Jonathan Rose · 2000 · 284 citations · Full text
Performance-driven placement of cell based IC's
M.A.B. Jackson, E.S. Kuh · 1989 · 184 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17
Timing driven placement for large standard cell circuits
W. H. Swartz, Carl Sechen · 1995 · 172 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +11
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University of Minnesota
Minneapolis, United States
12 h-index
33 publications
1.3K citations
University of California San Diego
San Diego, United States
11 h-index
25 publications
1.3K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
11 h-index
32 publications
2.8K citations
Intel (United States)
Santa Clara, United States
10 h-index
25 publications
800 citations
IBM (United States)
Armonk, United States
10 h-index
21 publications
745 citations
University of California, Los Angeles
Los Angeles, United States
10 h-index
19 publications
610 citations
University of California, Berkeley
Berkeley, United States
8 h-index
20 publications
1.4K citations
IBM Research - Austin
Austin, United States
7 h-index
15 publications
410 citations
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15 publications · 834 citations
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ICCAD · 5 publications · 228 citations
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Conference · 3 publications · 152 citations
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3 publications · 42 citations
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Conference · 3 publications · 197 citations
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