IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1998 · 64 citations · 20 references
EngineeringComputer EngineeringComputer ScienceFault-tolerant ComputingFault-tolerant SystemsField-programmable Gate ArraysBuilt-in Self-testDesign For TestabilityFault DetectionField-programmable Gate Array ArchitectureFpga ArchitectureHardware Fault ToleranceFault SimulationField-programmable Gate Arrays (Fpgas)Hardware DiagnosticsHardware Fault DetectionScan-based Self-checkingSelf-test Architecture
We introduce a technique for on-line built-in self-testing (BIST) of bus-based field programmable gate arrays (FPGAs). This system detects deviations from the intended functionality of an FPGA without using special-purpose hardware, hardware external to the device, and without interrupting system operation. Such a system would be useful for mission-critical applications with resource constraints. The system solves these problems through an on-line fault scanning methodology. A device's internal resources are configured to test for faults. Testing scans across an FPGA, checking a section at a time. Simulation on a model FPGA supports the viability and effectiveness of such a system.
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