IEEE Transactions on Device and Materials Reliability · 2006 · 179 citations · 24 references
EngineeringVlsi DesignEnergy EfficiencyComputer ArchitectureCmos CircuitsLong-term ReliabilityPower ElectronicsReliability EngineeringAdvanced Packaging (Semiconductors)Electronic PackagingElectrical EngineeringHardware ReliabilityBias Temperature InstabilityComputer EngineeringSelf-heating EffectHeat TransferDevice ReliabilityMicroelectronicsBulk Cmos TechnologiesTechnology Feature SizeTechnology ScalingCircuit ReliabilityThermal EngineeringBeyond Cmos
As the technology feature size is reduced, the thermal management of high-performance very large scale integrations (VLSIs) becomes an important design issue. The self-heating effect and nonuniform power distribution in VLSIs lead to performance and long-term reliability degradation. In this paper, we analyze the self-heating effect in high-performance sub-0.18-/spl mu/m bulk and silicon-on-insulator (SOI) CMOS circuits using fast transient quasi-dc thermal simulations. The impact of the self-heating effect and technology scaling on the metallization lifetime and the gate oxide time-to-breakdown (TBD) reduction are also investigated. Based on simulation results, an optimized clock-driver design is proposed. The proposed layout reduces the hot-spot temperature by 15/spl deg/C and by 7/spl deg/C in 0.09-/spl mu/m SOI and bulk CMOS technologies, respectively.
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