High-performance microprocessor design

P.E. Gronowski, William J. Bowhill, R.P. Preston, +2

IEEE Journal of Solid-State Circuits

EngineeringVlsi DesignElectronic DesignComputer ArchitectureProcessor Architecture +16

Superscalar instruction execution in the 21164 Alpha microprocessor

J.H. Edmondson, P.I. Rubinfeld, R.P. Preston, +1

IEEE Micro

Superscalar Alpha MicroprocessorEngineeringComputer ArchitectureIntegrated CircuitsProcessor Architecture +16

A 300-MHz 64-b quad-issue CMOS RISC microprocessor

B.J. Benschneider, Andrew J. Black, William J. Bowhill, +18

IEEE Journal of Solid-State Circuits

Low-power ElectronicsSystem On ChipElectrical EngineeringEngineeringVlsi Design +8

Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading

R.P. Preston, R.W. Badeau, Dan Bailey, +15

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

Manycore ProcessorEngineeringHigh-performance ArchitectureAlpha Instruction SetComputer Architecture +10

A 433-MHz 64-b quad-issue RISC microprocessor

P.E. Gronowski, William J. Bowhill, D.R. Donchin, +9

IEEE Journal of Solid-State Circuits

Low-power ElectronicsSystem On ChipElectrical EngineeringHardware SecurityChip Implementation Details +10

A 300 MHz 64 b quad-issue CMOS RISC microprocessor

William J. Bowhill, R. Allmon, Shane Bell, +13

Hardware SecuritySystem On ChipElectrical EngineeringChip-scale PackageEngineering +13

Circuit design guidelines for n-channel MOSFET hot carrier robustness

K. Mistry, T.F. Fox, R.P. Preston, +3

IEEE Transactions on Electron Devices

EngineeringVlsi DesignTransistor LevelPower ElectronicsElectromagnetic Compatibility +16

Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading

R.P. Preston, R.W. Badeau, Dan Bailey, +15

Manycore ProcessorEngineeringHigh-performance ArchitectureAlpha Instruction SetComputer Architecture +10

A 433 MHz 64 b quad issue RISC microprocessor

P.E. Gronowski, Peter Bannon, M.S. Bertone, +17

Low-power ElectronicsSystem On ChipElectrical EngineeringEngineeringVlsi Design +8

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node

Giuliano Sisto, R.P. Preston, Rongmei Chen, +11