A 300-MHz 64-b quad-issue CMOS RISC microprocessor

TLDR

The paper details the circuit and implementation techniques used to achieve a 300 MHz operating frequency. Fabricated in a 3.3 V, four‑layer metal, 0.5 µm CMOS process, the chip uses metal‑3 and metal‑4 for power, ground, and clock distribution, supports 3.3 V/5.0 V interfaces, is packaged in a 499‑pin ceramic IPGA, and includes an 8‑kB instruction cache, an 8‑kB dual‑ported data cache, and a 96‑kB unified second‑level 3‑way set‑associative write‑back cache. The 300 MHz quad‑issue Alpha implementation achieves 1200 MIPS peak, 600 MFLOPS peak, 341 SPECint92, and 512 SPECfp92, on a 16.5 mm × 18.1 mm die with 9.3 million transistors and 50 W dissipation.

Abstract

This 300 MHz quad-issue custom VLSI implementation of the Alpha architecture delivers 1200 MIPS (peak), 600 MFLOPS (peak), 341 SPECint92, and 512 SPECfp92. The 16.5 mm/spl times/18.1 mm die contains 9.3 M transistors and dissipates 50 W at 300 MHz. It is fabricated in a 3.3 V, four-layer metal, 0.5 /spl mu/m, CMOS process. The upper metal layers (metal-3 and metal-4), primarily used for power, ground, and clock distribution. The chip supports 3.3 V/5.0 V interfaces and is packaged in a 499-pin ceramic IPGA. It contains an 8-kbyte instruction cache; an 8-kbyte, dual-ported, data cache; and a 96-kbyte, unified, second-level, 3-way set associative, fully pipelined, writeback cache. This paper describes the circuit and implementation techniques that were used to attain the 300 MHz operating frequency.