2002 · 167 citations · 12 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsDesign For TestabilityLow-power Digital Circuit DesignPower EstimationPower ManagementPower OptimizationPower-aware DesignLow-power Design For TestabilityPower ConsumptionPower Consumption ModelingPower Management TechniquesPower Reduction AnalysisPower Reduction TechniquesSwitching Activity AnalysisSwitching Activity Reduction
Power consumption during scan testing is becoming a concern. Circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption. This paper presents a scheme for reducing power and provides analysis results on an industrial design.
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Combinational profiles of sequential benchmark circuits
F. Brglez, D. Bryan, Krzysztof Koźmiński · 2003 · 2.1K citations
V. Dabholkar, S. Chakravarty, Irith Pomeranz et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1998 · 320 citations
Adapting scan architectures for low power operation
L. Whetsel · 2002 · 268 citations
Engineering, Computer Engineering, Electrical Engineering +12