Time Dependent Vccmin Degradation of SRAM Fabricated with High-k Gate Dielectrics

Abstract

The paper presents the results of simulations of voltage-induced V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ccmin</sub> drift of SRAMs fabricated with high-k gate dielectrics. The authors show that high-k based SRAMs are fundamentally more susceptible to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ccmin</sub> stability problems because PMOS NBTI and NMOS PBTI lead to an additive degradation in the bit-cell read voltage. Given the differing time dependences of the NBTI and PBTI phenomena, the drift of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ccmin</sub> is enhanced at much earlier times compared to SRAMs that have SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric only devices. Maintaining V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ccmin</sub> stability presents a significantly greater challenge for high-k gate dielectrics compared to SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub>