2004 · 11 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ReliabilityEmbedded Memory BlocksIntegrated Circuit DesignMemory DevicesMemory Subsystem DesignEmbedded MemoryLow-voltage Cmos DesignMemory Circuit DesignNon-volatile Cmos MemoryNon-volatile MemoryNon-volatile Memory DesignSiliconThreshold Voltage
A new Local SONOS structure has been proposed for an embedded NVM cell in 0.13 /spl mu/m standard CMOS logic process. The localized storage silicon nitride layer of Local SONOS cell provides the essential properties for the embedded NVM such as the complete erase, low program current, and high on cell current from the low threshold voltage. The entire embedded memory solution has been realized with 0.276 /spl mu/m/sup 2/ Local SONOS NVM cell, which has 20 /spl mu/s program and 2 ms erase speed under 5.5 V bias condition, and good reliability without the special algorithms and cell array modifications.
2
NROM: A novel localized trapping, 2-bit nonvolatile memory cell
B. Eitan, Paolo Pavan, I. Bloom et al. · IEEE Electron Device Letters · 2000 · 547 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +12
Michael White, Dennis A. Adams, Jianhui Bu · IEEE Circuits and Devices Magazine · 2000 · 399 citations
Engineering, Computer Engineering, Electrical Engineering +17