IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2012 · 15 citations · 8 references
EngineeringComputer EngineeringComputer ScienceField-programmable Gate ArraysHardware Description LanguagesReconfigurable ComputingConfigurable Logic BlocksField-programmable Gate Array ArchitectureFpga ArchitectureLogic SynthesisLookup TablesRouting ArchitectureAdaptive Logic ModelsArea OptimizationArea-efficient Fpga ArchitectureBounded-depth CircuitsCut-based MappingDepth ReductionLogic Function ImplementationTechnology Mapping To Logic Blocks
Modern field programmable gate arrays like Altera's Stratix Series have adopted the adaptive logic module (ALM) structure due to its potential performance and area advantages. An ALM can implement a single logic function or can be fractured into two smaller lookup tables (LUTs). In this paper, we propose an ALM mapping algorithm, ALMmap, for area minimization with bounded depth. We revamp the traditional iterative cut-based mapping flow and introduce a procedure for bounded depth mapping generation with dynamic area recovery that effectively combines cut selection, mapping, and area recovery together. In addition, we introduce a new procedure for computing cut set for ALM minimization under a depth constraint. The notion of area flow which has been used successfully for cut selection to reduce LUT count is revised for cut selection to reduce ALM count. ALMmap obtains depth optimal solutions that are 25.6% and 11.6% smaller, on average, than those produced by a classical mapper and WireMap, respectively.
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SIS : A System for Sequential Circuit Synthesis
Ellen Sentovich · 1992 · 1.9K citations
Jason Cong, Chang Wu, Yuzheng Ding · 1999 · 194 citations