Z.G. Vranesic - Concepedia

Author

Z.G. Vranesic

Also Known As

Z Vranesic, Z. G. VRANESIC, Z. G. Vranesic, Z. Vranesic, Z.G. Vranesic, Zvonko G. Vranesic, Zvonko Vranesic, z.g. vranesic

132

Publications

3.8K

Citations

H-Index

Concepts

All Affiliations

University of Toronto McGill University

About

Z.G. Vranesic is an author at University of Toronto specializing in computer engineering, engineering, and computer science.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	26	49	2.3K
2	Computer Engineering	26	46	2.3K
3	Computer Science	24	41	2.1K
4	Electrical Engineering	5	5	154
5	Intellectual Property	1	1	68

Z.G. Vranesic

Publications

2.4K

Citations

H-Index

Page 1

	Year	Citations
Chortle-crf: Fast technology mapping for lookup table-based FPGAs Robert J. Francis, Jonathan Rose, Z.G. Vranesic Hardware SecurityLogic SynthesisChortle-crf ProgramEngineeringHardware Acceleration	1991	261
A detailed router for field-programmable gate arrays Stephen D. Brown, Jonathan Rose, Z.G. Vranesic IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringDetailed Routing AlgorithmPathfindingNetwork RoutingComputer Architecture	1992	153
Technology mapping of lookup table-based FPGAs for performance Robert J. Francis, Jonathan Rose, Z.G. Vranesic EngineeringVlsi DesignTechnology MappingHardware AlgorithmComputer Architecture	1991	139
The multicluster architecture: reducing cycle time through partitioning Keith I. Farkas, Paul Chow, Norman P. Jouppi, Cluster ComputingEngineeringComputer ArchitectureProcessor ArchitectureCluster Technology	2002	129
Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping Valavan Manohararajah, Stephen D. Brown, Z.G. Vranesic IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems CartographyDuplication-free Mapping ModesEngineeringHardware AlgorithmComputer Engineering	2006	124
Memory-system design considerations for dynamically-scheduled processors Keith I. Farkas, Paul Chow, Norman P. Jouppi, Hardware SecurityMemory-system Design ConsiderationsEngineeringHardware AccelerationEdge Computing	1997	105
Hector: a hierarchically structured shared-memory multiprocessor Z.G. Vranesic, Michael Stumm, David Lewis, Computer EngineeringComputer ArchitectureSystem-level DesignInterconnection Network ArchitectureEmbedded Systems	1991	103
On Fault Detection in CMOS Logic Networks Kuang-Wei Chiang, Z.G. Vranesic Design Automation Conference EngineeringVerificationComputer ArchitectureNetwork AnalysisFormal Verification	1983	80
A Many-Valued Algebra for Switching Systems Z.G. Vranesic, Ethan Lee, K.C. Smith IEEE Transactions on Computers Many-valued AlgebraAlgebraic LogicEngineeringFunctional Basic SetComputer Engineering	1970	79
The NUMAchine multiprocessor R. Grindley, Tarek S. Abdelrahman, Stephen D. Brown, Cluster ComputingNumachine MultiprocessorEngineeringComputer ArchitectureInterconnection Network Architecture	2002	75

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