Valavan Manohararajah

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

Valavan Manohararajah, Stephen D. Brown, Z.G. Vranesic · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2006 · 127 citations

Engineering, Computer Engineering, Computer Science +16

The Stratix™ 10 Highly Pipelined FPGA Architecture

David Lewis, Gordon R. Chiu, Jeffrey Chromczak et al. · 2016 · 70 citations

Engineering, Computer Engineering, Computer Science +17

Incremental retiming for FPGA physical synthesis

Deshanand P. Singh, Valavan Manohararajah, Stephen D. Brown · 2005 · 21 citations

Engineering, Computer Engineering, Computer Science +17

Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2007 · 20 citations

Engineering, Computer Engineering, Computer Science +14

Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh et al. · 2006 · 19 citations

Engineering, Computer Engineering, Computer Science +15