Toward System on Chip (SoC) Development Using FinFET Technology: Challenges, Solutions, Process Co-Development & Optimization Guidelines

TLDR

The study investigates how process/technology co‑optimization affects SoC performance in nanoscale FinFETs, examines an implant‑free CMOS process for better scalability, and proposes a modification to further improve logic and analog performance. The authors analyze FinFET optimization challenges with standard ion implantation for overlap and underlap designs, evaluate an implant‑free CMOS process, and suggest a process modification to enhance logic and analog performance. FinFETs fabricated with the implant‑free process exhibit roughly a two‑fold improvement in SRAM and digital I/O performance.

Abstract

In this paper, the impact of process/technology co-optimization on System-on-Chip (SoC) performance using detailed 3-D process/device simulations has been studied for nanoscale FinFET devices. We investigated challenges in FinFET device optimization and scaling while using standard ion implantation process for both overlap and underlap designs. Moreover, an implant-free (IF) complementary metal-oxide-semiconductor process is discussed for better scalability with improved performance. FinFETs designed using this IF process shows a ~2× improvement in static random-access memory and digital input/ output performance. Additionally, a modification to the IF process is proposed, which further helps in achieving an improved logic and analog performance for overall SoC development.