A large σV<inf>TH</inf>/VDD tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme

Abstract

This paper demonstrates for the first time quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large σV <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> /VDD conditions. Since Z8T uses only 1T for each decoupled read-port, faster 2T differential sensing (D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> S) can be implemented within the same area as the single-ended DS8T. Thanks to D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> S, Z8T cell enables much faster R/W speed at VDDmin than DS8T. For the same VDDmin/speed, Z8T save the cell area by 15%. A fabricated 256-row 32Kb Z8T SRAM, using a 65nm low-power process, is 14% smaller area and 53% faster than DS8T SRAM, and is 430mV lower VDDmin than 6T-SRAM. The 32-row 4Kb Z8T macro achieves 250mV VDDmin.