Process variation in embedded memories: failure analysis and variation aware architecture

TLDR

Scaling to sub‑50‑nm devices amplifies dopant‑induced threshold‑voltage variations, especially in minimum‑geometry SRAM cells, causing many memory cells to fail. The study investigates SRAM cell failures due to process variation and introduces a variation‑aware cache architecture for high‑performance systems. The architecture adaptively resizes the cache to bypass faulty cells, incurring negligible energy and area overhead while remaining transparent to the processor. Experimental results show the design yields 93 % versus 33 % for the original cache, with only 1.5 % and 5.7 % average CPU performance loss for data and instruction caches, respectively, on the worst‑case fault‑tolerant chips.

Abstract

With scaling of device dimensions, microscopic variations in number and location of dopant atoms in the channel region of the device induce increasingly limiting electrical deviations in device characteristics such as threshold voltage. These atomic-level intrinsic fluctuations cannot be eliminated by external control of the manufacturing process and are most pronounced in minimum-geometry transistors commonly used in area-constrained circuits such as SRAM cells. Consequently, a large number of cells in a memory are expected to be faulty due to process variations in sub-50-nm technologies. This paper analyzes SRAM cell failures under process variation and proposes new variation-aware cache architecture suitable for high performance applications. The proposed architecture adaptively resizes the cache to avoid faulty cells, thereby improving yield. This scheme is transparent to processor architecture and has negligible energy and area overhead. Experimental results on a 32 K direct map L1 cache show that the proposed architecture can achieve 93% yield compared to its original 33%. The Simplescalar simulation shows that designing the data and instruction cache using the proposed architecture results in 1.5% and 5.7% average CPU performance loss (over SPEC 2000 benchmarks), respectively, for the chips with maximum number of faulty cells which can be tolerated by our proposed scheme.