2003 · 87 citations · 7 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingFault-tolerant SystemsMicroelectronicsBuilt-in Self-testCmos Circuit DesignDelay ModelingDesign For TestabilityFault DiagnosisReliable System DesignCmos Logic CircuitsCmos Logic DesignCombinational Logic DesignDelay Fault TestingPath Delay AnalysisPath Delay ModelingTiming Faults
The authors propose an integrated approach to the design of combinational logic circuits in which stuck-open faults and path delay faults are detectable by robust tests that detect modeled faults independent of the delays in the circuit under test. They demonstrate that the proposed designs and tests guarantee the design of CMOS logic circuits in which all path delay faults are locatable. >
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Model for Delay Faults Based Upon Paths
Gordon L. Smith · International Test Conference · 1985 · 710 citations
Easily Testable Realizations ror Logic Functions
S.M. Reddy · IEEE Transactions on Computers · 1972 · 278 citations