2002 · 22 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsCmos Circuit DesignConfigurable Logic BlocksDesign For TestabilityDigital Logic DesignCarry Lookahead AdditionCarry-lookahead LogicCmos Logic CircuitsHigh PerformanceLatch DesignReset LogicScan Chain DesignScan Design
Register circuitry is described which is suitable for use with Self Resetting CMOS (SRCMOS) logic. It is level sensitive scan design (LSSD) compatible and complies with and implements the SRCMOS test modes. The register has been coupled to a novel high performance self resetting incrementer, which is based on a carry lookahead tree implemented in negative logic, and with a strobed final sum circuit. Hardware measurements are presented, showing a 900 ps 58-bit incrementer delay.
1
A half-micron CMOS logic generation
Charles W. Koburger, William F. Clark, J. Adkisson et al. · IBM Journal of Research and Development · 1995 · 41 citations
Engineering, Computer Engineering, Electrical Engineering +15