Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

TLDR

The study describes the device physics of uniaxial strained silicon transistors. The design examines pattern sensitivity and mobility/Rext partitioning. Uniaxial strain yields higher PMOS drive current (0.72 mA/µm), faster inverter delays (4.6 ps), and enables 50 Mb SRAMs at 0.65 V, while being more effective, less costly, and easier to implement.

Abstract

We describe the device physics of uniaxial strained silicon transistors. Uniaxial strain is more effective, less costly and easier to implement. The highest PMOS drive current to date is reported: 0.72mA/ /spl mu/m. Pattern sensitivity and mobility/Rext partitioning are discussed. Finally we measure inverter delays as low as 4.6pS, and show 50Mb SRAMs operational at 0.65V.