A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth, +25

IEEE Transactions on Electron Devices

Electrical EngineeringEngineeringNanoelectronicsStress-induced Leakage CurrentApplied Physics +8

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

T. Ghani, M Armstrong, C. Auth, +17

Silicon Cmos TransistorsEngineeringHigh VolumeSilicon On InsulatorSemiconductor Device +15

A Logic Nanotechnology Featuring Strained-Silicon

Scott E. Thompson, M Armstrong, C. Auth, +16

IEEE Electron Device Letters

Electrical EngineeringEngineeringFlexible ElectronicsPhysicsNanoelectronics +10

High performance fully-depleted tri-gate CMOS transistors

B.S. Doyle, Suman Datta, M. Doczy, +7

IEEE Electron Device Letters

Electrical EngineeringEngineeringVlsi DesignNanoelectronicsBias Temperature Instability +9

A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell

Scott E. Thompson, N. Anand, M Armstrong, +41

Nm Logic TechnologyEngineeringVlsi DesignEdge 90Computer Architecture +17

A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm/sub 2/ SRAM cell

Peng Bai, C. Auth, S. Balakrishnan, +32

Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignChannel Strain +13

High performance 32nm logic technology featuring 2<sup>nd</sup> generation high-k + metal gate transistors

P. Packan, Sheikh A. Akbar, M Armstrong, +36

Nm Logic TechnologyElectrical EngineeringEngineeringVlsi DesignNanoelectronics +11

A 32nm logic technology featuring 2<sup>nd</sup>-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm<sup>2</sup> SRAM cell size in a 291Mb array

S. Natarajan, M Armstrong, M. Bost, +40

EngineeringVlsi DesignChannel StrainIntegrated CircuitsSemiconductor Device +15

Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

K. Mistry, M Armstrong, C. Auth, +11

Electrical EngineeringEngineeringVlsi DesignNanoelectronicsSilicon Transistors +11

30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays

R. Chau, J. Kavalieros, B. Roberds, +7

Electrical EngineeringEngineeringVlsi DesignNanoelectronicsBias Temperature Instability +9