A. Murthy

A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Transactions on Electron Devices · 2004 · 654 citations

Electrical Engineering, Engineering, Nanoelectronics +10

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

T. Ghani, M Armstrong, C. Auth et al. · 2004 · 559 citations

Silicon Cmos Transistors, Engineering, High Volume +17

A Logic Nanotechnology Featuring Strained-Silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Electron Device Letters · 2004 · 511 citations

Electrical Engineering, Engineering, Flexible Electronics +12

High performance fully-depleted tri-gate CMOS transistors

B.S. Doyle, Suman Datta, M. Doczy et al. · IEEE Electron Device Letters · 2003 · 453 citations

Electrical Engineering, Engineering, Vlsi Design +11

A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell

Scott E. Thompson, N. Anand, M Armstrong et al. · 2003 · 241 citations

Nm Logic Technology, Engineering, Vlsi Design +19