S. Cea

A 90-nm logic technology featuring strained-silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Transactions on Electron Devices · 2004 · 654 citations

Electrical Engineering, Engineering, Nanoelectronics +10

A Logic Nanotechnology Featuring Strained-Silicon

Scott E. Thompson, M Armstrong, C. Auth et al. · IEEE Electron Device Letters · 2004 · 511 citations

Electrical Engineering, Engineering, Flexible Electronics +12

A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell

Scott E. Thompson, N. Anand, M Armstrong et al. · 2003 · 241 citations

Nm Logic Technology, Engineering, Vlsi Design +19

Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

K. Mistry, M Armstrong, C. Auth et al. · 2004 · 153 citations

Electrical Engineering, Engineering, Vlsi Design +13

Physics of Hole Transport in Strained Silicon MOSFET Inversion Layers

E.X. Wang, Philippe Matagne, L. Shifren et al. · IEEE Transactions on Electron Devices · 2006 · 143 citations

Electrical Engineering, Engineering, Physics +12