IEEE Transactions on Nuclear Science · 2013 · 52 citations · 20 references
EngineeringComputer EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice ScalingHeavy-ion PhysicsHighly Charged IonsLinear Energy TransferVery-large-scale Integration LayoutDevice Scaling EffectsFlip-flop DesignFlip-flopsHeavy Ion RadiationLinear Energy Transfer EffectsRedundant Data StorageRedundant Storage ArchitecturesRedundant Storage Systems
Heavy-ion experimental results from flip-flops in 180-nm to 28-nm bulk technologies are used to quantify single-event upset trends. The results show that as technologies scale, D flip-flop single-event upset cross sections decrease while redundant storage node flip-flops cross sections may stay the same or increase depending on the layout spacing of storage nodes. As technology feature sizes become smaller, D flip-flop single-event upset cross sections approach redundant storage node hardened flip-flops cross sections for particles with high linear energy transfer values. Experimental results show that redundant storage node designs provide <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$> 100{\rm X}$</tex></formula> improvement in single-event upset cross section over DFF for ion linear energy transfer values below <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$10~\hbox{MeV-cm}^2/\hbox{mg}$</tex></formula> down to 28-nm feature sizes.
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Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices
N. Seifert, P. Slankard, Martin Kirsch et al. · 2006 · 203 citations
Engineering, Computer Engineering, Electrical Engineering +17