New test methodology for resistive open defect detection in memory address decoders

Abstract

Intra-gate resistive open defects not only cause sequential behaviour in CMOS memory address decoders, but also lead to delay behaviour. This paper evaluates the fault coverage of the resistive open defects in the memory address decoders. It shows that both the strong and the weak open defects are not completely covered by applying the well-known March tests and special test pattern sequences published in the literature. We demonstrate that the fault coverage is increased by varying the duty cycle of the internal clock of the address decoder. For the self-timed memories, we introduce a simple DFT technique to control the duty cycle of the internal clock which activates/deactivates the word lines. Using defect-oriented test, we also created a fault dictionary based on the defect location, transistor types, the terminal name and also the faulty behaviour. The fault dictionary in combination with the bit-map fail data will facilitate the localization of the open defects.