Analysis of the electrical breakdown in hydrogenated amorphous silicon thin-film transistors

Abstract

Electrical breakdown induced by systematic electrostatic discharge (ESD) stress of thin-film transistors used as switches in active matrix addressed liquid crystal displays has been studied using electrical measurements, electrical simulations, electrothermal simulations, and postbreakdown observations. Breakdown due to very short pulses (up to 1 /spl mu/s) shows a clear dependence on the channel length. A hypothesis that electrical breakdown in the case of short channel TFTs is due to the punch-through is built on this dependence and is proved by means of electrical simulations. Further, the presence of avalanche breakdown in amorphous silicon thin-film transistors is simulated and confirmed. It is finally assumed that the breakdown is a thermal process. Three-dimensional (3-D) electrothermal simulations are performed in the static and transient regime, confirming the location of the breakdown spot within the TFT from the electrical simulations and postbreakdown observations.