Wafer-scale modeling of pattern effect in oxide chemical mechanical polishing

Abstract

Dielectric film thickness variation arising from layout pattern dependency remains a major concern in oxide CMP. The severity of the pattern density effect is a function of the die location on the wafer, thus a combined wafer/die pattern dependent polishing model is required to fully assess the effectiveness of the process for a given planarization requirement. In this work, a two stage modeling methodology which accounts for both wafer-scale variation and within-die pattern dependencies, as well as their interaction, is developed. The effectiveness of the methodology is demonstrated over a range of polishing process conditions and consumable choices. We find that the integrated wafer/die CMP model accurately predicts the resulting increase or decrease in die-level pattern dependencies as a function of die position on the wafer.