High Performance Asynchronous Design Using Single-Track Full-Buffer Standard Cells

Abstract

This paper presents a high-performance asynchronous template, single-track full-buffer (STFB), which achieves close to full-custom performance using a standard cell design flow and industry standard CAD tools to perform schematic capture, simulation, cell layout, and automatic placement and routing. This template and flow is demonstrated and evaluated with the implementation of a 64-bit asynchronous prefix adder, and its test circuitry, using the TSMC 0.25-/spl mu/m process. The 64-bit asynchronous prefix adder layout requires 0.96 mm/sup 2/ and the entire 260-k transistor test chip reaches a measured throughput of 1.45GHz. The design demonstrates that the STFB template can yield three times higher throughput with approximately half of the area of comparable quasi-delay-insensitive (QDI) templates, requires less timing assumptions than ultra-high-speed GasP bundled-data circuits, and can be designed with an automated place and route flow.