GasP: a minimal FIFO control

TLDR

GasP is a family of asynchronous circuits that provide control for pipelines, branching, joining, scatter/gather, and on‑demand joins via arbitration. Each stage runs on a three‑inverter ring oscillator, with transistor widths tuned to equalize gate delays, enabling a single wire to carry request/ack and stage state signals and achieving >1.5 GDI/s throughput in 0.35 µm technology. Uniform gate delays enable self‑resetting logic with very low logical effort.

Abstract

The GasP family of asynchronous circuits provides controls for simple pipelines, for branching and joining pipelines, for round-robin scatter and gather for data dependent scatter and gather and for join on demand through arbitration. The family is designed so that each stage operates at the speed of a three-inverter ring oscillator Test chips in 0.35 micron technology exhibit throughput in excess of 1.5 giga data items per second (GDI/s). Between GasP pipeline stages a single wire carries both request and acknowledge messages, also recording the FULL or EMPTY state of each pipeline stage. GasP control circuits rely on careful choice of transistor widths to equalize the delay in logic gates. Assurance of uniform gate delays permits use of self-resetting logic forms that have very low logical effort.