IEEE Journal of Solid-State Circuits · 1982 · 36 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ReliabilityLow-power Digital Circuit DesignMemory DevicesMemory ManagementMemory Subsystem DesignDynamic Power DissipationDynamic Random-access MemoryLow-power Memory ArchitectureMemory Circuit DesignPolysiliconRandom Access Memory (Ram)Random-access MemorySense Amplifier Design
A 5 V 256K/spl times/1 bit NMOS dynamic RAM employing redundancy is described. Using 2.3 /spl mu/m design rules, the cell is laid out in a folded bit line configuration having a row pitch of 6.5 /spl mu/m and a sense-amplifier pitch of 18 /spl mu/m. Tantalum silicide/polysilicon is used as the second polysilicon level to reduce the row line time constant. A storage capacitance of 60 fF and the Hi-C cell structure provides this memory with high alpha-particle insensitivity. The die measures 4.66/spl times/11.65 mm, and fits into a standard 0.3 in wide 16-pin DIP. The memory operates with 256 refresh cycles with a 4 ms refresh time. Typical RE/CE access times are 105/45 ns with an active power dissipation of 250 MW. Typical standby power is less than 20 mW. The part is compatible with the present Western Electric 5 V 64K part.
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A fault-tolerant 64K dynamic random-access memory
R.P. Cenker, D.G. Clemons, W.R. Huber et al. · IEEE Transactions on Electron Devices · 1979 · 96 citations
A fault-tolerant 64K dynamic RAM
R.P. Cenker, D.G. Clemons, W.R. Huber et al. · 1979 · 66 citations
Engineering, Computer Engineering, Electrical Engineering +16