2007 · 91 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice CharacterizationDevice ReliabilityLeakage Power ReductionLow-power Digital Circuit DesignMos CapacitorsCapacitorsGate LeakageGate Leakage CurrentGate Oxide LeakageGate Oxide Leakage ReductionLeakage Current ModelingLeakage-constrained Circuit DesignUltra-low-power Cmos
In this work, we present a novel ultra-low power timer designed using the gate leakage of MOS capacitors. The test chip was fabricated in a 0.13 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m CMOS technology and the total circuit area is 480 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">μ</i> m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Measurement results show that the circuit functions correctly at a wide range of supply voltages from 300mV to 1.2V, making it particularly suitable for subthreshold systems. The temperature sensitivity is 0.16%/°C at 600mV and 0.6%/°C at 300mV. The power dissipation is less than 1pW running at 20°C and 300mV.
6
BSIM4 gate leakage model including source-drain partition
A 2.60pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency
Bin Zhai, Leyla Nazhandali, Javin Olson et al. · 2006 · 183 citations
Engineering, Computer Engineering, Electrical Engineering +17
All-CMOS temperature independent current reference
C.-H. Lee, H.-J. Park · Electronics Letters · 1996 · 72 citations