2008 · 12 citations · 1 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsRisk AssessmentSemiconductor DevicesDevice ModelingDevice ReliabilityDevice SimulationIntegrated Circuit DesignReliability ModelingSemiconductor ReliabilityCmos ReliabilityCmos ScalingHot Carrier EffectsHot Carrier GenerationHot Carrier InjectionHot-carrier DegradationLifetime EstimationReliability Simulation
The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of refined transistor HC modeling, Wafer Level Reliability (WLR) & High Temperature Operating Lifetest (HTOL) experimental results and simulations.
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K. Hess, Leonard F. Register, Blair Tuttle et al. · Physica E Low-dimensional Systems and Nanostructures · 1998 · 51 citations