Assessment of the DPI Standard for Immunity Simulation of Integrated Circuits

Abstract

Ensuring immunity to electromagnetic interference (EMI) is a major challenge in present designs. Making integrated circuits intrinsically less susceptible to interference by adapted circuit design, can reduce costs substantially in later stages. It is shown that small changes in the circuit topology can increase the immunity of IC's by several order of magnitude. Being able to predict whether a chip will pass susceptibility tests before fabrication, is essential in order to reduce costs. For this reason, accurate simulation of the standard test methods, is needed. In this paper, a simulation framework is presented that allows accurate simulation and prediction of the IEC62132-4 DPI standard.