Characterization and Modeling of Parasitic Emission in Deep Submicron CMOS

Abstract

This paper presents a study of the parasitic emissions of a 0.18-/spl mu/m CMOS experimental integrated circuit (IC) and an accurate method for modeling the internal current switching to forecast electromagnetic interference (EMI). The effectiveness of emission reduction techniques is quantified through a set of conducted noise measurements. A simple core model is developed, based on the current switching activity. Added to a lumped-element model of the test board and the package, good agreement between simulation and measurements are obtained up to 10 GHz. The simulation methodology may be applied to forecast the impact of low emission design techniques on the EMI of ICs.