EngineeringComputer EngineeringComputer SystemsComputer NetworksHardware-software Co-designSystem-on-chip DesignBuilt-in Self-testDesign For TestabilityInterconnect ArchitectureNetwork ArchitectureNetwork-on-chip DesignPacket SwitchingBuilt-in Test ArchitectureCommunication System TestingInterconnect CharacterizationNetwork TestingNetwork-on-chip ArchitecturesNetwork-on-chip TestabilitySystem-level TestabilityTest Access Mechanism Design
In this paper, a Test Access Mechanism (TAM) architecture based on a packet switching communication network is presented. The basic goal is to develop a modular, generic, and configurable TAM.The proposed architecture provides a modular TAM that provides two levels of scalability, i.e., design-version scalability and multi-level scalability. Core access time and interconnect length models and simulation results for the proposed architecture are presented and compared to that of a bus- based TAM.
12
Testing embedded-core based system chips
Y. Zorian, Erik Jan Marinissen, S. Dey · 2002 · 427 citations
Engineering, Computer Engineering, Electrical Engineering +15
A structured and scalable mechanism for test access to embedded reusable cores
Erik Jan Marinissen, R. Arendsen, G. G. J. Bos et al. · 2002 · 344 citations
A structured test re-use methodology for core-based system chips