Network-on-chip Testability

Network-On-Chip Testability is a design-for-testability methodology that enables the systematic verification and fault detection of interconnection networks within multi-core integrated circuits by incorporating dedicated test structures and protocols to ensure reliable communication fabric operation.

76

Publications

2.3K

Citations

154

Authors

72

Institutions

Publications per year

2017–2026

7

Authors

154

  1. ÉC
    Érika Cota

    Universidade Federal do Rio Grande do Sul, Brazil

    9 publications · 449 citations

    9

    h-index

  2. AI
    A. Ivanov

    University of British Columbia, Canada

    7 publications · 508 citations

    7

    h-index

  3. BB
    Biswajit Bhowmik

    National Institute of Technology Karnataka, India

    7 publications · 105 citations

    7

    h-index

  4. SB
    Santosh Biswas

    Indian Institute of Technology Guwahati, India

    7 publications · 105 citations

    7

    h-index

  5. ML
    Marcelo Lubaszewski

    Universidade Federal do Rio Grande do Sul, Brazil

    7 publications · 311 citations

    7

    h-index

1–5 of 154

Venues

  1. Journal of Electronic Testing

    JETTA · 4 publications · 67 citations

    4

    h-index

  2. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 3 publications · 44 citations

    3

    h-index

  3. IEEE Design & Test of Computers

    2 publications · 192 citations

    2

    h-index

  4. Design, Automation, and Test in Europe

    Conference · 2 publications · 49 citations

    2

    h-index

  5. 2

    h-index

1–5