Network-on-chip Testability
Network-On-Chip Testability is a design-for-testability methodology that enables the systematic verification and fault detection of interconnection networks within multi-core integrated circuits by incorporating dedicated test structures and protocols to ensure reliable communication fabric operation.
76
Publications
2.3K
Citations
154
Authors
72
Institutions
Publications per year
2017–2026
7
Parents
76
Design, Synthesis, and Test of Networks on Chips
Partha Pratim Pande, Cristian Grecu, A. Ivanov et al. · IEEE Design & Test of Computers · 2005 · 175 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17
A scalable test strategy for network-on-chip routers
Alexandre M. Amory, Eduardo Brião, Érika Cota et al. · 2006 · 103 citations
BIST for Network-on-Chip Interconnect Infrastructures
Cristian Grecu, Partha Pratim Pande, A. Ivanov et al. · 2006 · 90 citations
1–5 of 76
154
9
h-index
7
h-index
7
h-index
7
h-index
7
h-index
1–5 of 154
72
Universidade Federal do Rio Grande do Sul
Porto Alegre, Brazil
11 h-index
42 publications
2.2K citations
Indian Institute of Technology Guwahati
Guwahati, India
7 h-index
18 publications
281 citations

University of British Columbia
Vancouver, Canada
6 h-index
18 publications
1.5K citations
Tsinghua University
Beijing, China
5 h-index
10 publications
122 citations

Washington State University
Pullman, United States
4 h-index
4 publications
391 citations
Laboratoire de Conception et d'Intégration des Systèmes
Valence, France
4 h-index
8 publications
160 citations
Duke University
Durham, United States
4 h-index
7 publications
102 citations
Tallinn University of Technology
Tallinn, Estonia
4 h-index
12 publications
393 citations
1–8 of 72
JETTA · 4 publications · 67 citations
4
h-index
TODAES · 3 publications · 44 citations
3
h-index
2 publications · 192 citations
2
h-index
Conference · 2 publications · 49 citations
2
h-index
2 publications · 105 citations
2
h-index
1–5