IEEE Transactions on Nuclear Science · 1996 · 126 citations · 23 references
EngineeringComputer EngineeringElectrical EngineeringFault ToleranceMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice ReliabilityDevice ScalingIntegrated Circuit DesignRadiation HardeningSemiconductor ReliabilityCmos ReliabilityCmos ScalingDevice Scaling EffectsGate Oxide ScalingHardnessRadiation-hardened Integrated CircuitsRadiation-hardening TechniquesScaling Effects In Cmos
The impact of technology trends on the SEU hardness of epitaxial CMOS SRAMs is investigated using three-dimensional simulation. We study trends in SEU susceptibility with parameter variations across and within technology generations. Upset mechanisms for various strike locations and their dependence on gate-length scaling are explored. Such studies are useful for technology development and providing input for process and design decisions. An application of SEU simulation, to the development of a 0.5-/spl mu/m radiation-hardened CMOS SRAM is presented.
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Physics of Semiconductor Devices
Samarth Jain, S. Radhakrishna · 1987 · 4.2K citations
Rate prediction for single event effects-a critique
E.L. Petersen, J.C. Pickel, James H. Adams et al. · IEEE Transactions on Nuclear Science · 1992 · 279 citations