A 2500 gate bipolar macrocell array with 250 ps gate delay

Abstract

An oxide-isolated walled-emitter structure has been developed to obtain high performance and high packing density. Using this process, a macrocell array having 2500 equivalent gates has been fabricated. A gate delay of 250 ps with a 1 mA current switch has been achieved. Special circuitry and macros have been incorporated on the LSI to enhance diagnostic capability at both the chip and the system levels. A pin array package with /spl theta//SUB JA//spl les/4/spl deg/C/W has been developed for the LSI chip.