Gate Array Design

Gate Array Design is a semiconductor design methodology that belongs to the class of application-specific integrated circuit (ASIC) implementation approaches, distinguished by its use of predefined, repeated transistor arrays on a silicon substrate that are customized in the final metal interconnect layers to realize specific logic functions.

298

Publications

10.5K

Citations

1.1K

Authors

199

Institutions

Publications per year

2017–2026

20

Authors

1.1K

  1. MW
    Minoru Watanabe

    Shizuoka University, Japan

    16 publications · 401 citations

    12

    h-index

  2. LT
    Louise Trevillyan

    IBM Research - Thomas J. Watson Research Center, United States

    4 publications · 107 citations

    4

    h-index

  3. VR
    Vyacheslav Rovner

    Carnegie Mellon University, United States

    4 publications · 276 citations

    4

    h-index

  4. AJ
    Andrzej J. Strojwas

    Carnegie Mellon University, United States

    4 publications · 249 citations

    4

    h-index

  5. LT
    Lawrence T. Pileggi

    Carnegie Mellon University, United States

    4 publications · 195 citations

    4

    h-index

1–5 of 1.1K

Venues

  1. IEEE Journal of Solid-State Circuits

    35 publications · 1.3K citations

    18

    h-index

  2. 10

    h-index

  3. Applied Optics

    7 publications · 158 citations

    7

    h-index

  4. Design Automation Conference

    Conference · 6 publications · 182 citations

    6

    h-index

  5. Proceedings of the IEEE

    5 publications · 231 citations

    5

    h-index

1–5