Gate Array Design
Gate Array Design is a semiconductor design methodology that belongs to the class of application-specific integrated circuit (ASIC) implementation approaches, distinguished by its use of predefined, repeated transistor arrays on a silicon substrate that are customized in the final metal interconnect layers to realize specific logic functions.
298
Publications
10.5K
Citations
1.1K
Authors
199
Institutions
Publications per year
2017–2026
20
298
Fast Regular Expression Matching Using FPGAs
Reetinder Sidhu, Viktor K. Prasanna · 2001 · 533 citations
J.A. Waicukauski, Eric Lindbloom, Barry K. Rosen et al. · IEEE Design & Test of Computers · 1987 · 402 citations
Engineering, Computer Engineering, Electrical Engineering +16
The Design of Special-Purpose VLSI Chips
Kung · Computer · 1980 · 231 citations
Engineering, Computer Engineering, Electrical Engineering +16
1–5 of 298
1.1K
12
h-index
IBM Research - Thomas J. Watson Research Center, United States
4 publications · 107 citations
4
h-index
4
h-index
4
h-index
4
h-index
1–5 of 1.1K
199
IBM (United States)
Armonk, United States
13 h-index
41 publications
2.4K citations

Shizuoka University
Shizuoka, Japan
13 h-index
31 publications
835 citations
Texas Instruments (United States)
Dallas, United States
10 h-index
53 publications
1.4K citations
Toshiba (Japan)
Tokyo, Japan
10 h-index
62 publications
1.2K citations
Carnegie Mellon University
Pittsburgh, United States
9 h-index
56 publications
3.3K citations
Mitsubishi Electric (Japan)
Tokyo, Japan
9 h-index
51 publications
1.4K citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
9 h-index
36 publications
1.3K citations
Hitachi (Japan)
Tokyo, Japan
7 h-index
48 publications
741 citations
1–8 of 199
35 publications · 1.3K citations
18
h-index
11 publications · 858 citations
10
h-index
7 publications · 158 citations
7
h-index
Conference · 6 publications · 182 citations
6
h-index
5 publications · 231 citations
5
h-index
1–5