A parasitic extraction method of VLSI interconnects for pre-route timing analysis

Abstract

For faster timing closure, a parasitic extraction method is developed for the pre-route VLSI design. This method generates virtual route and estimates congestion using the placement information of standard cells, and then extract the interconnect parasitics with the pattern-library method. The techniques of generating parasitic RC tree according to the improved FLUTE algorithm, and capacitance extraction of route segment considering congestion are presented. Experiments are carried out on industrial design cases, whose results show that the proposed method has high computational speed and comparable accuracy as commercial tool.