28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder

Abstract

A minimum design effort methodology to enable energy efficient and variability tolerant ultra-wide voltage-range frame error-decoder design in 28nm CMOS technology is presented. Critical aspects of a digital design development - standard cells, interface, clock tree and implementation - were optimized enabling 1.0V to 350mV functionality, 10x energy reduction, 10MHz to 700MHz frequency, and a reduction of the variability enabling industrial yield at ultra-low voltage. The same design was then ported to 28nm Fully-Depleted SOI (FDSOI), offering up-to 2x higher energy efficiency while validating the design methodology robustness.