2010 · 18 citations · 15 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureHardware Description LanguagesHardware-software Co-designClock ManagementDesign For TestabilityHardware DebuggingAt-speed TestingDebug AutomationFunctional Design PatternsLeading-edge DesignPerformance DebuggingScan Chain DebuggingScan Chain TestingSilicon Debugging
Speedpath debug is a critical step in improving clock frequency of a design to meet the performance requirement. However, speedpath debug based on functional patterns can be very expensive. In this paper, we explore scan-based speedpath debug techniques based on at-speed scan test patterns. Several enhancements are implemented to improve over an earlier proposed scan-based speedpath diagnosis algorithm. We further report the application results by applying the improved algorithm to a leading-edge high performance microprocessor design.
15
On Silicon-Based Speed Path Identification
L. Lee, Li-C. Wang, P. Parvathala et al. · 2005 · 42 citations
Enhancing Transition Fault Model for Delay Defect Diagnosis
Wu-Tung Cheng, Brady Benware, Ruifeng Guo et al. · 2008 · 38 citations
Engineering, Computer Engineering, Electrical Engineering +17
Data learning techniques and methodology for Fmax prediction
Janine Chen, Li-C. Wang, Po-Hsien Chang et al. · 2009 · 38 citations