Scan Chain Debugging
Scan Chain Debugging is a hardware debugging method that enables the observation and control of internal circuit states through a serially connected chain of flip-flops, distinguished by its use of scan-based test architecture to facilitate fault detection and diagnosis in digital integrated circuits.
21
Publications
695
Citations
62
Authors
25
Institutions
Publications per year
2017–2026
2
Parents
21
An efficient scheme to diagnose scan chains
Sridhar Narayanan, Anirban Das · 2002 · 106 citations
Engineering, Computer Engineering, Electrical Engineering +17
1–5 of 21
62
2
h-index
IBM Research - Thomas J. Watson Research Center, United States
2 publications · 72 citations
2
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2
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IBM Research - Thomas J. Watson Research Center, United States
2 publications · 72 citations
2
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2
h-index
1–5 of 62
25
Advanced Micro Devices (United States)
Sunnyvale, United States
2 h-index
5 publications
76 citations

University of Cincinnati
Cincinnati, United States
2 h-index
4 publications
76 citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
2 h-index
6 publications
216 citations
Infineon Technologies (Germany)
Munich, Germany
2 h-index
3 publications
52 citations
Mentor Technologies
Tulsa, United States
2 h-index
6 publications
94 citations

University of Vermont
Burlington, United States
2 h-index
2 publications
72 citations
Philips (Netherlands)
Amsterdam, The Netherlands
2 h-index
7 publications
287 citations
Oracle (United States)
Austin, United States
2 h-index
4 publications
162 citations
1–8 of 25
2 publications · 99 citations
2
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VTS · 1 publications · 13 citations
1
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Conference · 1 publications · 11 citations
1
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1 publications · 15 citations
1
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Conference · 1 publications · 16 citations
1
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1–5