Scan Chain Debugging

Scan Chain Debugging is a hardware debugging method that enables the observation and control of internal circuit states through a serially connected chain of flip-flops, distinguished by its use of scan-based test architecture to facilitate fault detection and diagnosis in digital integrated circuits.

21

Publications

695

Citations

62

Authors

25

Institutions

Publications per year

2017–2026

2

Authors

62

  1. JW
    Jing Wang

    Capital Normal University, China

    2 publications · 29 citations

    2

    h-index

  2. FS
    Franco Stellari

    IBM Research - Thomas J. Watson Research Center, United States

    2 publications · 72 citations

    2

    h-index

  3. MM
    Michael Mateja

    Advanced Micro Devices (United States), United States

    2 publications · 29 citations

    2

    h-index

  4. PS
    Peilin Song

    IBM Research - Thomas J. Watson Research Center, United States

    2 publications · 72 citations

    2

    h-index

  5. KT
    Karen Tomko

    Ohio Supercomputer Center, United States

    2 publications · 38 citations

    2

    h-index

1–5 of 62

Venues