Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

T. Shino, N. Kusunoki, Tomoki Higashi, Takashi Ohsawa, K. Fujita, Kosuke Hatsuda, Nobuyuki Ikumi, Fumiyoshi Matsuoka, Yasuyuki Kajitani, Ryo Fukuda,

2006 · 33 citations · 2 references

Concepts

Abstract

Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant

References

2