Concepedia

Yasuyuki Kajitani

YK

Statistics

Publications

8

Citations

305

H-Index

8

Active since

2006

Affiliations

Toshiba (Japan)(Current)

Western Digital (United States)

Yasuyuki Kajitani is an author at Toshiba (Japan) specializing in electrical engineering, memory subsystem design, and engineering.

Publications per year

2006–2019

8

Publications

8

13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology

Chang Siau, Kwang Ho Kim, Seungpil Lee et al. · 2019 · 85 citations

Engineering, Computer Engineering, Electrical Engineering +15

A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology

Noboru Shibata, K. Kanda, Takahiro Shimizu et al. · IEEE Journal of Solid-State Circuits · 2019 · 56 citations

Engineering, Computer Engineering, Electrical Engineering +13

13.1 A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology

Noboru Shibata, K. Kanda, Tatsuo Shimizu et al. · 2019 · 50 citations

Engineering, Computer Engineering, Electrical Engineering +14

A 113mm2 32Gb 3b/cell NAND flash memory

T. Futatsuyama, Norihiro Fujita, Naoya Tokiwa et al. · 2009 · 37 citations

Engineering, Computer Engineering, Electrical Engineering +16

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

T. Shino, N. Kusunoki, Tomoki Higashi et al. · 2006 · 33 citations

Engineering, Computer Engineering, Electrical Engineering +16

1–5 of 8