Simulation based transistor-SRAM co-design in the presence of statistical variability and reliability

Abstract

We report on a systematic simulation study of the impact of process and statistical variability and reliability on SRAM cell design in a 14nm technology node SOI FinFET transistors. A comprehensive statistical compact modelling strategy is developed for early delivery of a reliable PDK with built-in statistical variability and reliability information. This enables TCAD-based transistor-SRAM co-design and path finding for emerging technology nodes.