2014 · 33 citations · 16 references
EngineeringComputer EngineeringElectrical EngineeringFault ToleranceLow-power DesignMicroelectronicsClock GatingDevice ReliabilityHardware Fault ToleranceLow-power Digital Circuit DesignRadiation HardeningTiming AnalysisClock Gating For Digital CircuitsLatch DesignLow-power Latch DesignRadiation-hard ElectronicsRadiation-hardening TechniquesRadiation-tolerant ElectronicsSoft Error MitigationSoft Errors
As technology node entered the era of nanotechnology, a latch is much more susceptible to soft errors caused by energetic particles in space radiation environment. In order to enhance the Single Event Upset (SEU) -tolerance capability of a latch, this paper presents an interlocking soft error hardened latch (ISEHL) which is suitable for low-power circuits. The proposed latch is based on three C-elements which are errors tolerable, and the logic state of each C-element is determined by the output state of two other C-elements, which constitute an interlocking soft error hardened latch. The simulation results show that the proposed ISEHL latch can not only be applied to clock-gating circuits but also perform with 41% power as well as 95% Power Delay Product (PDP) saving as comparing with the FERST latch which performs an equivalent superior SEU-tolerance ability.
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Soft Errors in Advanced Computer Systems
R. Baumann · IEEE Design & Test of Computers · 2005 · 832 citations