Single-Event Tolerant Flip-Flop Design in 40-nm Bulk CMOS Technology

Abstract

In this paper, the radiation response of a single-event tolerant flip-flop design named the Quatro flip-flop is presented. Circuit level simulations on the flip-flop design show 1) the critical charge of the sensitive nodes to be greater than that of DICE flip-flop, 2) the number of sensitive nodes and the sensitive area to be fewer than that of DICE flip-flop. A test-chip designed and fabricated at the 40-nm bulk CMOS technology node consisting of Quatro, DICE, and standard D- flip-flops was used for heavy-ions, neutrons, and alpha particles exposures. The experimental results demonstrate superior performance of the Quatro flip-flop design over conventional DICE and D-flip-flop designs.