2013 · 17 citations · 8 references
EngineeringSilicon ViasIntegrated CircuitsThermal ConductivityGold NanoparticlesInterconnect (Integrated Circuits)Wafer Scale ProcessingAdvanced Packaging (Semiconductors)Inkjet-printed Gold NanoparticlesMaterials FabricationPrinted ElectronicsElectronic PackagingNanolithography MethodMaterials ScienceHeterogeneous Mems IntegrationNanotechnologyNanomanufacturingThermal TransportChip AttachmentMicroelectronicsAdvanced PackagingMicrofabricationNanomaterialsApplied PhysicsNanofabricationThermocompression Bond Bumps
We present a novel technique for heterogeneous integration using gold filled Through Silicon Vias (TSV) and thermocompression bond bumps formed in a single fabrication step, using gold nanoparticles dispensed by inkjet printing. Gold-filled TSV arrays (12 × 12, via radius 50μm, pitch 250μm) have been demonstrated using this method. Void free, filled TSVs are reported, and thermocompression bonding yielded seamless interfaces. Die shear tests show good bond strength, and sub-Ω via resistances were measured. The presented integration process exhibits a low temperature budget (≤250°C), allows good alignment, and is compatible with substrates of different sizes and materials, enabling the heterogeneous integration of known-good-dies (KGD) which may have been fabricated in different technologies.
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8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology
Uksong Kang, Hoeju Chung, Seongmoo Heo et al. · IEEE Journal of Solid-State Circuits · 2010 · 484 citations
Makoto Motoyoshi · Proceedings of the IEEE · 2009 · 464 citations
A wafer-scale 3-D circuit integration technology
J.A. Burns, Brian F. Aull, C.K. Chen et al. · IEEE Transactions on Electron Devices · 2006 · 265 citations
3D Ic Architecture, Electrical Engineering, Wafer Scale Processing +15