A diagonal active-area stacked capacitor DRAM cell with storage capacitor on bit line

Abstract

A stacked-capacitor (STC) cell concept for 16-Mb DRAMs is introduced. The STC cell features a storage capacitor placed on a bit line and a diagonal active area. This enables a large storage capacitance, 35 fF/b, to be achieved on a 3.36- mu m/sup 2/ cell. By eliminating completely the structural interferences between bit line and plate electrode, the storage-node pattern is maximized. The STC cell also features low noise characteristics due to its shielded bit-line structure. This minimizes the interbit-line capacitance to below 1% of the bit-line capacitance in the memory array. The average charge retention time, measured using an experimental 2-kb array, is 30 s at 40 degrees C. The characteristics of the diagonal active memory cell transistor are comparable to those of a conventional transistor.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>