IEEE Transactions on Electron Devices · 1987 · 20 citations · 9 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignLow-noise Circuit DesignNoise In Electronic DevicesNoise In Semiconductor DevicesCircuit SimulationHeterostructure TransistorsLogic GatesMosfet NoiseNoise In Field-effect TransistorsNoise Margin AnalysisNoise MarginsSurface Potential
A complementary logic circuit employing heterostructure MISFET's is shown to have a larger logic swing and noise margin than an E/D MESFET logic circuit. The noise margin is calculated using a new gate current model that is derived by taking into account the small surface potential dependence on the gate voltage at the heterointerface. The circuit simulation indicates that, for multi-input logic gates, a NAND gate configuration is superior to a NOR gate configuration from the viewpoints of noise margin and switching speed. The normalized high- and low-level noise margins are comparatively balanced (34 and 49 percent) for a three-input NAND gate. For a fan-in/fan-out of 3/3 and a 100-fF wiring capacitance condition, a 54-ps delay time and 57-μW power dissipation/gate at a 100-MHz clock frequency are possible for a NAND gate with 0.5-μm gate-length MISFET's at 77 K.
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A GaAs gate heterojunction FET
P. M. Solomon, C. M. Knoedler, Steven L. Wright · IEEE Electron Device Letters · 1984 · 116 citations
Complementary heterostructure insulated gate field effect transistors (HIGFETs)
N.C. Cirillo, M. S. Shur, P.J. Vold et al. · 1985 · 28 citations