Turn-Around of Threshold Voltage in Gate Bias Stressed p-Channel Power Vertical Double-Diffused Metal–Oxide–Semiconductor Transistors

Abstract

The "turn-around" of threshold voltage in high gate electric field stressed p-channel power vertical double-diffused metal–oxide–semiconductor (VDMOS) transistors was observed and analyzed in details. This unexpected effect was observed only in devices stressed by enough high positive gate voltages, leading to the gate electric fields above 6.3 MV/cm, and it was more pronounced in those stressed by higher voltages, when threshold voltage shift exhibited very strong dependence on stressing time. The quantitative analysis of the results obtained revealed that stress-induced instabilities of the gate oxide charge and interface traps, due to a complex electrochemical processes occurring in the gate oxide and at silicon–oxide interface during the stressing, were responsible for the observed "turn-around" effect.