High-current, small parasitic capacitance MOS FET on a poly-Si interlayered (PSI: Ψ) SOI wafer

M. Horiuchi, Toshiaki Teshima, Kazuya Tokumasu, Ken Yamaguchi

2002 · 12 citations · 6 references

Concepts

Abstract

An ultra-thin SOI MOSFET capable of operations at a current 1.5 times that of conventional deep sub-micron devices at low voltage is presented. This device is fabricated by a conventional MOS process on novel multi-layered SOI wafers.

References

6