2002 · 30 citations · 16 references
EngineeringComputer EngineeringComputer ScienceFault ToleranceFault-tolerant ComputingFault-tolerant SystemsDesign For TestabilityError DetectionHardware Fault ToleranceReliable System DesignSelf-checking CircuitsTiming AnalysisAsynchronous Self-checking CircuitsDelay-insensitive CircuitsDigital Circuit Self-testingFault Secure CircuitsFormal Specification Of Combinational CircuitsPermanent FaultsSelf-checking DesignSelf-checking Logic
Considers designing quasi-delay-insensitive (QDI) combinational circuits (CCs), a class of self-timed (asynchronous) circuits. The necessity of coding both inputs and outputs of any QDI CC by using unordered codes naturally leads to inverter-free realization. The analysis of behavior of a QDI CC with input errors leads to the observation that it is impossible to avoid the so-called late detection problem. The new set of correct definitions of the code-disjoint QDI CC and of the totally self-checking (TSC) QDI CC is introduced. The detailed analysis of the behavior of a faulty QDI system with internal permanent faults shows that: (1) late detection, (2) the possibility of occurrence of invalid transitions, and (3) premature completion, seem to be the inherent properties of any QDI CC, which preclude its fault-secure (hence TSC) implementation for some single stuck-at faults. The first ever self-testing code-disjoint completion checker is proposed. Finally, an extensive study of designing self-testing code-disjoint QDI CCs is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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